1. Field of the Invention
The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly to method for manufacturing a CMOS image sensor in which ions implanted during formation of low-concentration n-type and p-type dopant regions for forming a photodiode are prevented from penetrating under a gate electrode, so that generation of a leakage current can be restrained.
2. Description of the Prior Art
In general, an image sensor is a semiconductor device for converting an optical image into an electrical signal, and is generally divided into CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor) image sensors.
The CCD is a device in which charge carriers are stored and transferred under the situation that each MOS capacitor is closely disposed to each other, while the CMOS image sensor is a device employing a switching mode of forming as many MOS transistors as the number of pixels using CMOS technology, which makes use of controlling and signal processing circuits as periphery circuits, to detect outputs using the MOS transistors.
The CCD has various disadvantages, such as complicated drive mode, much power consumption, impracticability or impossibility of fabricating a signal processing circuit in the same chip as the CCD due to many mask processes, and so on. Currently, in order to overcome these disadvantages, many studies have been made in the development of the CMOS image sensor using sub-micron CMOS manufacturing technology.
The CMOS image sensor obtains an image by forming a photodiode and a MOS transistor within a unit pixel to detect signals in a switching mode. As mentioned above, because the CMOS image sensor makes use of CMOS manufacturing technology, the CMOS image sensor has little power consumption as well as a simple manufacturing process requiring about 20 masks, compared with the CCD manufacturing process requiring 30 to 40 masks. As a result, the CMOS image sensor can integrate a signal processing circuit into a single chip, so that it is possible to make a product compact, thereby allowing for many applications.
Hereinafter, a description will be made regarding a construction of the CMOS image sensor. FIGS. 1 and 2 are a circuit diagram and a layout diagram showing a structure of a unit pixel of the conventional CMOS image sensor. For the sake of reference, the number of transistors constituting the CMOS image sensor is three or more. However, for the sake of convenience of description, the CMOS image sensor with three transistors alone will be mainly described.
As shown in FIGS. 1 and 2, a unit pixel 100 of the CMOS image sensor comprises a photodiode 110 as a means for sensing light and three NMOS (N-channel Metal Oxide Semiconductor) transistors. Among the three transistors, one is a reset transistor (Rx) 120, which functions not only to transfer optical charges generated from the photodiode 110 but also to discharge charges so as to detect signals, another is a drive transistor (Dx) 130, which functions as a source follower, and the third is a select transistor (Sx) 140, which performs switching and addressing functions.
Meanwhile, in the CMOS image sensor of the unit pixel, the photodiode 110 is designed to function as a source of the reset transistor (Rx) 120 in order to facilitate movement of the charges. To this end, in the course of manufacturing the image sensor of the unit pixel, a process of implanting low- or high-concentration dopant ions into a location including a part of the photodiode 110 is used as shown in FIG. 2. The manufacturing process will be described with reference to a cross-section taken along line A-A′ of FIG. 2. For the sake of reference, the solid lines in FIG. 2 indicate a boundary or interface of an active region 160.
First, as shown in FIG. 3a, a gate insulation layer 122 and a gate electrode 123 are sequentially formed on a p-type semiconductor substrate 101, on which an element isolation layer 121 is completely formed using shallow trench isolation (STI) and the like. Here, even though not shown, a p-type epitaxial layer may be previously formed within the p-type substrate. Subsequently, a photosensitive layer is applied on the front surface of the substrate, and then a pattern for the photosensitive layer, which defines a region of the photodiode, is formed using a photolithography process. Here, the photosensitive layer pattern does not expose the gate electrode.
In this state, low-concentration dopant ions, for example n-type dopant ions, are implanted into the substrate, so that there is formed a low-concentration dopant region n− having a predetermined depth in the substrate.
Next, as shown in FIG. 3b, another photosensitive layer pattern 125 which does not expose the low-concentration (n−) dopant region is formed, and then another low-concentration dopant region 115 for an LDD structure is formed in a drain region of the electrode using the photosensitive layer pattern 125 as an ion implantation mask.
Subsequently, as shown in FIG. 3c, spacers 126 are formed on a side wall of the gate electrode, and then a p-type dopant region 110 (“p0”) is formed on the n-type dopant region n− and an n-type dopant region n+ is formed on the n(−)-type dopant region 115. Thereby, the process of forming the photodiode is completed. When the photodiode is finished, high-concentration dopant ions are selectively implanted to form a high-concentration dopant region n+ in the drain region of the gate electrode. As a result, the process associated with the cross-section taken along line A-A′ of FIG. 2 is terminated.
According to the conventional method for manufacturing the CMOS image sensor, in order to increase a sensitivity of the CMOS image sensor, a depth of the low-concentration n-type dopant region n− for forming the photodiode is greater than a height of the gate electrode. That is, when the height of the gate electrode is about 2000 Å, the depth of the low-concentration n-type dopant region n− for forming the photodiode is set to about 3000 Å.
Meanwhile, a process of forming the low-concentration n-type dopant region n− for the photodiode (in a photodiode region defined by the gate electrode and the element isolating layer) is performed after the gate electrode is finished. Here, in order to prevent the low-concentration n-type dopant ions from being implanted into the active region below the gate electrode, the photosensitive layer pattern is formed over the gate electrode, but not over the photodiode region. At this time, one end of the photosensitive layer pattern is generally aligned to match with one end of the gate electrode.
The lithography process for forming the photosensitive layer pattern is composed of various unit processes, such as photoresist application, exposure, development, peeling, and so forth. An important factor for realizing a fine profile of the photosensitive layer is the exposure process. The exposure process makes use of ultraviolet (UV) or distant ultraviolet (DUV) rays as an exposure source, and exposes predetermined locations of the photosensitive layer to the rays. Recently, with high integration of semiconductor devices, a wavelength of the exposure source shows a tendency to be shortened. Presently, an I-line, which is broadly used as the exposure source, has a wavelength of 365 nm.
As mentioned above, when the photosensitive layer is patterned using the I-line as the exposure source, a deviation of about 0.15 μm is generated between an initially set profile and formed photosensitive layer pattern by influences such as the I-line irradiation wavelength (see FIG. 3d).
According to this technical basis, the photosensitive layer pattern, as an ion implantation mask, formed on the gate electrode during formation of the low-concentration n-type dopant region n− for the photodiode has one end, which may not be exactly matched with a corresponding end of the gate electrode, so that two ends show a difference of up to about 0.15 μm to each other.
Thus, during an actual ion implantation process, one end of the low-concentration n-type dopant region may not be exactly aligned with the corresponding end of the gate electrode, and implanted ions penetrate under the gate electrode pattern to a predetermined extent. This is because the photosensitive layer pattern exposes up to about 0.15 μm of the gate electrode, and the depth b of the low-concentration dopant region n− is larger than the height a of the gate electrode. Further, as mentioned above, the low-concentration dopant region n− may also penetrate under the gate electrode to a predetermined extent from an influence of subsequent annealing or heat treatment.
In this manner, as the low-concentration dopant region n− overlaps a lower region of the gate electrode, a channel under the gate electrode becomes shortened. As a result, short channel effects and possibly other detriments) are incurred, which can generate a leakage current.